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1.
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Half
adder circuit is ______?
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(a) Half of an AND gate
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(b) Half of a NAND gate
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(c) A circuit to add two bits
together
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(d) none of above
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2.
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If one wants to design a binary
counter, preferred type of flip-flop is
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(a) D-type
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(b) SR-type
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(c) Latch
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(d) JK-type
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3.
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A flip-flop is a binary cell
capable of storing _____________ bit of information.
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(a) three
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(b) one
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(c) two
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(d) four
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4.
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Which of the following flip-flops
is free from race around problem?
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(a) T flip-flop
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(b) SR flip-flop
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(c) Master-Slave Flip-flop
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(d) none
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5.
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S-R type flip-flop can be converted
into D type flip-flop if S is connected to R through
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(a) OR Gate
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(b) Inverter
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(c) AND Gate
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(d) Full Adder
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6.
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A particular Full Adder has |
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(a) 3 inputs and 2 output
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(b) 3 inputs and 3 output
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(c) 2 inputs and 3 output
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(d) 2 inputs and 2 output
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7.
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If an S-R latch has a 1 on the S
input and a 0 on the R input and then the S input goes to 0, the latch will
be
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(a) Set
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(b) Reset
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(c) Indeterminate
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(d) Complement
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8.
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Which of the following is the
Universal Flip-flop?
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(a) SR Flip-flop
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(b) JK Flip-flop
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(c) Master slave
Flip-flop
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(d) D Flip-flop
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9.
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How is the JK Flip-flop made
to toggle?
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(a)
J=0, K=0
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(b)
J=1,
K=0
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(c)
J=1,
K=1
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(d)
J=0,
K=1
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10.
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Full adder is
constructed by using …………….
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(a)
Two Half Adder& one OR gate.
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(b)
Two
OR gate &one HA
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(c)
One
HA & two OR gate.
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(d)
One
OR gate & one HA
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11.
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A D flip-flop can be made from a
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(a)
JK flip-flop and an inverter
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(b) RS flip-flop
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(c) RS flip-flop and an inverter
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(d) both (a) and (b).
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12.
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How is a J-K flip-flop made to toggle? |
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(a) J = 0, K = 0 |
(b) J = 1, K = 0 |
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(c) J = 0, K = 1 |
(d) J = 1, K = 1 |
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13.
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A J-K flip-flop is in a
"no change" condition when ________.
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(a) J = 1, K = 1
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(b) J = 1, K = 0
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(c) J = 0, K = 1
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(d) J = 0, K = 0
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14.
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A
set of flip flops integrated together is called ____
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(a) Counter |
(b) Adder |
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(c) Register |
(d) None of the above
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15.
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Half-Adder Logic circuit contains
_____ XOR Gates.
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(a) 1 |
(b) 2 |
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(c) 4 |
(d) 6
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Computer Organization and Architecture MCQ -2
